ECEn 320

Seven Segment Controller

Purpose: The purpose of this laboratory is to design a 7 segment controller in VHDL, simulate the design in ModelSim, synthesize the design using XST, and demonstrate the 7 segment decoder operating on your FPGA prototyping board. We will use this seven segment controller throughout the semester.


In ECEN 224 you created a 224 4x7 segment controller lab as part of a timer. This controller performed several functions including decoding binary signals and generating the corresponding 7-segment display signals and driving the anode signals. We will build a similar 4x7 segment controller in VHDL. The design in this lab, however, is slightly different than the approach taken in 224.

Before proceeding, carefully read pages 17-19 of the Spartan-3 Board User's Manual. This section describes the 7-segment display and how it must be driven. Answer each of the following questions on the Blackboard lab write-up assignment before proceeding with the lab.

The architecture of the 4x7 segment decoder we will create in this lab is shown below. This decoder contains several different components. A counter is provided to provide the timing for the anode select lines (AN3-AN0). The top two bits of the counter are used to select the digit (and decimal point) that is driven on the display. Using the top-two bits of a binary counter ensures that each digit will be driven for the same amount of time. The amount of time each digit is driven is determined by the number of bits in the counter.

This controller also contains two multiplexers. One multiplexer is used to select the appropriate 4-bit segment input to display. This is a 4-bit, 4 to 1 multiplexer. The second multiplexer is used to select the appropriate decimal point to display. The controller also contains two decoders: one decoder is used to decode the four-bit value into the seven segment signals and the second decoder is used to decode the two-bit anode_select signal and generate the four independent anode control signals.

Design Exercise #1: Seven Segment Display Controller

Create a new VHDL file that contains the entity and architecture for your seven segment controller. Create an entity with the following input ports, output ports, and generics:

Port Bits Purpose
clk 1 Clock for segment counter
seg0[3:0] 4 Value to display on segment 0
seg1[3:0] 4 Value to display on segment 1
seg2[3:0] 4 Value to display on segment 2
seg3[3:0] 4 Value to display on segment 3
DP[3:0] 4 Value of the "decimal" points 

Port Bits Purpose
segments[6:0] 7 Segment control signals (i.e. A,B,C,D,E,F,G)
dp_out 1 Decimal point control signal
an_out[3:0] 4 Segment annode control signals (i.e. AN0, AN1, AN2, and AN3)

Generic Type Purpose Default
COUNTER_BITS NATURAL Indicates the number of bits on the segment counter 15

Create an empty architecture for your seven segment display controller. You will need to add a counter to your controller to sequence through the segments. Since you have not learned how to do this yet, the instructions below will describe how to add a counter to your design. First, add the following signal declaration into the declaration section of your architecture:

signal count : unsigned(COUNTER_BITS-1 downto 0) := (others => '0'); 

This declaration will declare a signal named count that will be used for the incrementing counter. Notice that the size of this signal is determined by the COUNTER_BITS generic. Once you have the signal declaration, add the following process to the body of the architecture. Since it is a concurrent statement, it does not matter where you put it:

  -- Counter operating at 50 MHz
  process (clk)
    if clk='1' and clk'event then
      count <= count+1;
    end if;
  end process;   

This process creates a counter that will increment every clock cycle. We will discuss this process in much more detail later during the semester. Assuming a 50 MHz clock and a 15-bit counter, how long will each digit of the display be driven by the controller? Record your answer in the blackboard write-up.

As shown in the diagram above, you will need to create an anode select signal (labeled anode_select in the figure) to select the appropriate anode to drive. This signal is also used to select the appropriate inputs of the two multiplexers. This signal should be created from the top two bits of the counter. Declare a two bit unsigned signal and assign it to the top two bits of the counter as shown below (note that this signal must be of type unsigned since the count type is unsigned). Notice how the generic value COUNTER_BITS is used to select the appropriate bits of the counter signal.

  -- Create the anode_select signal from the top two bits of the counter
anode_select <= count(COUNTER_BITS-1) & count(COUNTER_BITS-2);

With a working counter circuit, add all the other logic that is necessary for driving the signals of the seven segment controller. You will want to modify the default value of the COUNTER_BITS generic so you can see the anode_select signal change with less simulation time (if you do not lower this value, it will take a very long time to see the anode_select signal change). 

Create a testbench to simulate your seven segment controller. Apply several different inputs to the controller to verify that it operates as you expect it to. You will need to generate an oscillating clock signal to drive the clock for the counter. Include a concurrent statement like the following to generate an oscillating clock within your testbench:

clk <= not clk after 10 ns;

Simulate your seven segment contoller carefully to make sure it performs as you expect it - do not proceed with the lab until your seven segment display controller is operating correctly. Note that you will be using this component throughout the semester so put some time into the design to make sure it works correctly. Save your testbench file for this circuit so you can demonstrate your working simulation to the TA. You will need to submit both your seven segment display controller vhdl and your testbench vhdl code for the lab write-up.

Design Exercise #2: Package for VHDL components

For this laboratory, you will need to create a package that will contain the component declaration of your seven segment display. You will also need to expand this package throughout the semester and add the new components to the package that you create in future labs. Create your new package and compile it into your work library. When including your package for use in a module, remember that it is compiled to the work library.
  -- Sample package
  library ieee;
  use ieee.std_logic_1164.all
  package my320pkg is
    component Lab2_LED is
      port (
       switches : in std_logic_vector(3 downto 0);
       leds : out std_logic_vector(3 downto 0));
      end component Lab2_LED;
  end my320pkg;

Design Exercise #3: Top-Level Design file

The next step of the lab is to create a top-level design that uses your seven segment display controller. Create a separate vhdl file that instances your seven segment display and adds additional logic. You should use your package from the previous design exercise. The top-level design should do the following:

Design Suggestions:

  1. Simulate the design carefully. Do not attempt a download until you are convinced the circuit works in simulation. Remember to change the generic map value when you instance your display controller (use a small number for simulation, and use the default 15 bits for synthesis).
  2. Keep track of each bitfile that you synthesize (ideally, you will generate only one bitfile and it will work the first time). You will be required to indicate how many bitfiles you synthesized and provide a short description of what happened with each bitfile.
  3. Create a new Xilinx project for your design and include the three different vhdl files (the seven segment controller, the top level, and the package). You will need to manually create a .ucf file for this project.
  4. The name of your UCF file is important --- the extension must be ".ucf".  It turns out that the program that processes the UCF file is case-sensitive - it will not work with an extension of ".UCF".
  5. You MUST tell the Xilinx tools to use the JTAG clock instead of the main clock.  Otherwise your bitstream won't work.  To do this, in the Xilinx tools, right click the "Generate Programming File", select Properties, and then under "Startup Options", select "JTAG Clock".  Do this BEFORE you generate the bitstream for the first time.

Pass Off

Demonstrate the following to a TA to passoff your lab:

  1. Show your segment display controller simulation.
  2. Show the TA both vhdl files for your design (electronic is fine).
  3. Demonstrate to the TA a working circuit on your board.

Lab Write-Up

Complete your laboratory write-up on blackboard.