Introduction to ModelSim

Background

Logic simulators are an essential tool for any digital design project. Simulators provide visibility into all parts of your circuit and are necessary for verifying the correct operation of your circuit before synthesis. If their are problems in your circuit, it is far easier to identify them with a simulator than to find the problem after you have created your circuit. We will use the ModelSim simulator throughout semester to simulate the laboratory assignments and perform various experiments. To succeed in this course, it is essential that you learn to use ModelSim well and become familiar with its operation and function. While you will be given basic instruction on the use of ModelSim, you are strongly encouraged to learn more about the many features, capabilities, and tools that are a part of the ModelSim framework.

ModelSim is a sophisticated software tool that is used by many industry practitioners in the development of many large, complex digital circuits. ModelSim has been made available to us at the university at a fraction of the actual market cost. We appreciate the generosity of Mentor Graphics for providing ModelSim to the university for this educational experience.

Exercise 1 - Simulating a simple VHDL file

The first exercise will involve the simulation of a simple VHDL file in Modelsim. Create a new directory for this laboratory in your personal file space and copy the following files to this directory:

modelsim_intro1.vhd
modelsim_intro2.vhd
list_0207_even_tb.vhd

Begin this exercise by opening ModelSim. You can open ModelSim by clicking the ModelSim icon under "Programs" (this is found under Programs-> ECEN Programs-> Modelsim SE 6.4 -> Modelsim). Once ModelSim is open, create a new project in your file space: File -> New Project. In the dialog box, provide a name for the new project and select the location where you want the new project to be created (you should select the directory where you placed the files you copied from above). 

After clicking OK, you will be asked to add files to your project. Click "add existing file".

Once you have created the project, open the modelsim_intro1.vhd file using the File->open menu option. The VHDL file should be shown in a text editor with syntax highlighting. This VHDL file performs a simple Boolean "AND" function. For this exercise, you will simulate the VHDL file to convince yourself that the output operates as expected.

1. Compile modelsim_intro1.vhd.  This can be done several ways - you may want to try several of them out. You can type "vcom <filename>" in the command window or you can select the Compile->Compile menu button.
2. Begin simulation of this VHDL file. To do this, expand the "work" library in the Library tab and select the modelsim_intro1 entity. Right click it and select Simulate.  Note that the command vsim work.modelsim_intro1  appeared in the command ("Transcript") window.  Whenever you execute a command, you can usually find the corresponding text command in the transcript window. You can also initiate a simulation by typing the command in the transcript window.
3. A new set of windows will open up when the simulation begins. These windows include a list of signals and instances, a list of objects, and the original source. We want to open the waveform viewer to view the signals in this file. Once again there are multiple ways to do this. An easy way to do this is to click on the sim tab within the "Workspace" window.  Then click on modelsim_intro1. In the Objects window, you should see three things listed, namely input1, input2, and output.  Right-click on these and select Add to wave.  The wave window should then pop up with those three values there. Refer to the transcript window to see what commands can be used to perform the same function.
4. The waveform viewer is used to watch the behavior of the signals. To see something meaningful, we need to provide a stimulus on the inputs. By default, the inputs are assigned the value "U" (unknown). We will do this by "forcing" the input signals. Force the input1 signal to a 0 by typing the following command: "force input1 0". Force the input 2 signal to a 0 by running a similar command.
5. Next, run the simulator for a fixed amount of time to see the behavior of the output with these two inputs. Type the command: run 100ns to run the circuit for 100 ns. You should see the output signal change from a red line (meaning "X") to a valid green "0".
   
6. Test all four input conditions of this circuit to validate the behavior of the VHDL file. To do this, change the inputs using force commands and "run" the circuit for a fixed amount of time.

Exercise 2 - Writing simulation scripts

Scroll back through the "Transcript" window and see what the command arguments were that did your "force" and run commands. You can also see the commands you have run by running the "history" command line function. Create a .do file (such as intro1.do) in a text editor and type in all the commands needed to fully simulate this circuit. Here is an example of the opening lines of such a .do file:

quit -sim
vcom modelsim_intro1.vhd
vsim work.modelsim_intro1
add wave sim:/modelsim_intro1/input1
add wave sim:/modelsim_intro1/input2
add wave sim:/modelsim_intro1/output
# More commands for forcing and running

Run your ".do" simulation script (type do intro1.do in the command/Transcript window) and verify that the circuit functions as you expect it to do. Include a copy of your ".do" file in your laboratory writeup.

There are many commands you can use to aid in your circuit simulation and verification. You are encouraged to review the various commands in the ModelSim command . Also, the command interpreter used by ModelSim is based on Tcl (pronounced "tickle"). There are many native Tcl commands, control structures such as loops and procedures that can be used to help with your simulation runs. You may want to review the Tcl web site to learn more about the Tcl environment.

Exercise 3 - Fixing Compile Errors

This example is more complicated and performs an addition operation with multiple bit inputs.  You essentially need to follow the same directions as above, except there are a few wrinkles. Compile the modelsim_intro2.vhd file (note: you will get an error!).

1. When you compile, ModelSim will give you an error. Notice that all the information you are given is that there is 1 error. You can get even more information by changing an option in your project settings. First, make sure that your project tab is selected in the Workspace window. Then, on the toolbar, select Project->Project Settings. In the settings window, check "Display compiler output" and press OK.

2. Compile the modelsim_intro2.vhd file again. This time, notice that the line number of the error is given. Figure out where the error is and fix it. Recompile.
3. You are now dealing with an array of bits as opposed to a single bit.  Therefore, you can set the values in different ways than you could above.  For example, rather than typing in "11111111" in the "Force" Dialog box, you can type in 16#FF or 10#255.  Experiment with different ways.  Also, when watching the outputs of the wave window, you can right-click on the values, select radix, and have it display in different ways.  Once again, try it out.
4. Simulate several different values (at least ten) and verify that the circuit is operating as expected. Create a .do file to perform this test.

Exercise 4 - Simulating a new VHDL file

For this exercise, you will need to create a new VHDL file, compile it, and simulate it.

1. Create a new VHDL file by manually typing in the VHDL from Listing 2.1 from the textbook.
2. Compile the VHDL file using the Modelsim compiler
3. Simulate the the even-parity detector in Modelsim using your own  .do file. Provide at least five cases to demonstrate the circuit is working properly.

Exercise 5 - Simulating your VHDL file with a testbench

For this exercise, you will simulate the even detector VHDL file from the previous exercise using a testbench. 

1. Make sure you have downloaded the file list_0207_even_tb.vhd and add it to your project. This is listing 2.7 from the textbook. Open the file in Modelsim and review its contents. 
2. Compile this file. Note that this testbench will use the VHDL file you created in the previous exercise.
3. Simulate this testbench in Modelsim. You will need to start the simulation for the testbench, and then enter a "run" command in the command/Transcript window. Try to figure out how many nanoseconds the simulation needs to run. This testbench will exercise your even detector circuit much like the previous exercise. Note that this testbench performs many of the functions of the .do file.

Pass Off

Demonstrate your waveform and .do file for both Exercise 3 and Exercise 4. Have your waveforms and .do files ready when the TA comes to pass you off.

Lab Write-Up

Complete your laboratory write-up on blackboard.